1. Field of the Invention
The present invention relates to data processing systems and more particularly to data processing systems of the type having memory systems that interface with other parts of the data processing system.
2. Description of the Prior Art
There are many references in the prior art that relate to computing systems employing some form of memory sharing. Some examples follow.
U.S. Pat. No. 4,096,571 issued June 20, 1978 to Vander Mey, entitled SYSTEM FOR RESOLVING MEMORY ACCESS CONFLICTS AMONG PROCESSORS AND MINIMIZING PROCESSOR WAITING TIMES FOR ACCESS TO MEMORY BY COMPARING WAITING TIMES AND BREAKING TIES BY AN ARBITRARY PRIORITY RANKING, describes a computer system embodying four processor modules and four memory modules. The processors share the memory modules on a time shared basis. Bidirectional data transfers between memories and processors are accomplished by using a group of common signal lines called the address/data bus which supplies and transfers the data.
U.S. Pat. No. 4,257,095 issued March 17, 1981 to Nadir, entitled SYSTEM BUS ARBITRATION, CIRCUITRY AND METHODOLOGY describes a structure wherein a system bus and a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit which allows a lower priority processor or user to access the system bus during those times in which a higher priority user of the system bus is not actively accessing the system bus.
These two references are typical of shared bus systems and are distinct from the linked memory concept of the present invention.
U.S. Pat. No. 4,212,057 issued July 8, 1980 to Devlin et al and entitled SHARED MEMORY MULTI-MICROPROCESSOR COMPUTER SYSTEM describes a computer system having two or more substantially independent processors each of which has its own bus-type interconnection structure, and a shared memory accessible by any of the processors without interferring with the proper operation of the other processors. The shared memory may, if desired, appear to each of the two or more processors sharing it to be a different section of the total memory capability of the processor.
This reference describes a shared memory system which is quite different from the present invention. In the present invention the sharing is accomplished by using a special memory chip and each processor has access to a separate memory array. Communications between these arrays are mediated through the on-chip row buffer allowing a very wide data path width between the arrays.
In U.S. Pat. No. 4,212,057, the two processors share a common memory array with circuitry which merely provides access to the common array by both processors on a contention or priority basis.
U.S. Pat. No. 4,280,197 issued July 21, 1981 to Schlig and entitled MULTIPLE ACCESS STORE is cited because it shows a memory cell permitting simultaneous read/write functions which is, however, quite different from the present invention.
In addition to the prior art cited above, U.S. Pat. No. 4,541,075 issued Sept. 10, 1985 to Dill et al entitled QUASI TWO PORT MEMORY, filed June 30, 1982 describes a 256.times.256 bit array with row addresses applied thereto. Column addresses are applied to sense amplifiers and to a row buffer, a secondary port is provided and employed for improved efficiency of data transfer.